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acpl-302j 2.5 amp gate drive optocoupler with integrated flyback controller for isolated dc-dc converter, igbt desat detection, active miller clamping, fault and uvlo status feedback data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd. features ? integrated fyback controller for isolated dc-dc converter ? regulated output voltage: 20 v ? peak output current: 2.5 a max. ? miller clamp sinking current: 1.7 a max. ? wide input voltage range: 8 v to 18 v ? common-mode rejection (cmr): > 30 kv/ m s at v cm = 1500 v ? propagation delay: 250 ns max. ? integrated fail-safe igbt protection C desat detection, soft igbt turn-of and fault feedback C under voltage lock-out (uvlo) protection with feedback ? high noise immunity C miller current clamping C direct led input with low input impedance and low noise sensitivity C negative gate bias ? so-16 package with 8 mm clearance and creepage ? regulatory approvals: C ul 1577, csa C iec/en/din en 60747-5-5 applications ? isolated igbt/mosfet inverter gate drive ? renewable energy inverters ? ac and brushless dc motor drives ? industrial inverters ? uninterruptible power supplies (ups) description avago's acpl-302j 2.5 amp gate drive optocoupler features integrated fyback controller for isolated dc-dc converter, igbt desaturation sensing with fault feedback and soft-shutdown, under-voltage lockout (uvlo) with feedback and active miller current clamping. the fast propagation delay with excellent timing skew perfor - mance enables excellent timing control and efciency. this full feature optocoupler comes in a compact, surface- mountable so-16 package for space-savings, is suitable for driving igbts and power mosfets used in motor control and inverter applications. functional diagram figure 1. acpl-302j functional diagram lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product vee2 led2+ desat vcc2 vee2 vo vcc1 comp vee1 ca /fault ssd/ clamp /uvlo an osc r s uvlo over current input driver output driver sw ssd control miller control logic control ve
package outline drawing (16-lead surface mount) ordering information part number option (rohs compliant) package surface mount tape & reel iec/en/din en 60747-5-5 quantity acpl-302j -000e so-16 x x 45 per tube acpl-302j -500e x x x 850 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example: acpl-302j-500e to order product of so-16 surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval that is rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. recommended lead-free ir profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non-halide fux should be used. dimensions in millimeters (inches) note: lead coplanarity = 0.10 mm (0.004 inches) floating lead protrusion = 0.25 mm (0.010 inches) max. mold flash on each side = 0.127 mm (0.005 inches) max. recommended land pattern standoff 8.763 0.254 (0.345 0.010) 0.635 min. (0.025) 10.363 0.254 (0.408 0.010) 0.254 (0.010) 1.270 bsc (0.050) 0.457 typ. (0.018) 11.634 (0.458) 2.160 (0.085) (0 - 8) 9(4) 0.635 (0.025) 9(4) 3.505 0.127 (0.138 0.005) 0.203 0.102 (0.008 0.004) 7.493 +0.254 ?0.127 (0.295 10.363 (0.408 +0.010) ?0.005) +0.254 ?0.127 +0.010) ?0.005) 1.270 (0.050) typ. a 302j yyww type number date code eee lot id avago lead-free 2
figure 2. pinout of acpl-302j product overview description the acpl-302j (shown in figure 1) is a highly integrated power control device that incorporates all the necessary com - ponents for a complete, isolated igbt gate drive circuit. it features a fyback controller for isolated dc-dc converter, a high current gate driver, miller current clamping, igbt desaturation, under-voltage lock-out (uvlo) protection, and feedback in a so-16 package. direct led input allows fexible logic confguration and diferential current mode driving with low input impedance, greatly increases its noise immunity. pin description pin name function pin name function v ee1 input ic common v ee2 output ic common and negative power supply reference to igbt emitter sw switch output to primary winding led2+ no connection, for testing only v cc1 input power supply desat desat overcurrent sensing comp compensation network for flyback controller v e igbt emitter reference /uvlo v cc2 under voltage lock out feedback v cc2 positive power supply /fault overcurrent fault feedback v o driver output to igbt gate an input led anode ssd/clamp soft shutdown sensing/miller current clamping output. (for proper functionality, this pin must be connected to the gate of the igbt directly or through a current bufer.) ca input led cathode v ee2 negative power supply 16 15 14 13 12 11 10 9 led2+ vcc2 vee2 vee2 vo ve 1 2 3 4 5 6 7 8 sw vee1 an ca /fault /uvlo desat vcc1 comp ssd/clamp package pin out 3
typical application/operation introduction to fault detection and protection the power stage of a typical three-phase inverter is sus - ceptible to several types of failures, most of which are potentially destructive to the power igbts. these failure modes can be grouped into four basic categories: phase or rail supply short circuits due to user misconnect or bad wiring; control signal failures due to noise or computa - tional errors; overload conditions induced by the load; and component failures in the gate drive circuitry. under any of these fault conditions, the current through the igbts can increase rapidly, causing excessive power dissipation and heating. the igbts become damaged when the current load approaches the saturation current of the device, and the collector-to-emitter voltage rises above the saturation voltage level. the drastically increased power dissipation very quickly overheats the power device and destroys it. to prevent damage to the drive, fault protection must be implemented to reduce or turn of the overcurrent during a fault condition. a circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required compo - nents, board space consumed, cost, and complexity have until now limited its use to high performance drives. the features that this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. the acpl-302j satisfes these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local igbt de - saturation detection and shutdown, and optically isolated fault and uvlo status feedback signal into a single 16-pin surface mount package. the fault detection method, which the acpl-302j has adopted, is to monitor the saturation (collector) voltage of the igbt and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. a small gate discharge device slowly reduces the high short circuit igbt current to prevent damaging voltage spikes. before the dissipated energy can reach destructive levels, the igbt is shut of. during the of-state of the igbt, the fault detect circuitry is simply disabled to prevent false fault signals. the alternative protection scheme of measuring igbt current to prevent desaturation is efective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the igbt. by directly measuring the collector voltage, the acpl-302j limits the power dissipation in the igbt, even with insufcient gate drive voltage. another more subtle advantage of the desatu - ration detection method is that power dissipation in the igbt is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. therefore, an overly- conservative overcurrent threshold is not needed to protect the igbt. recommended application circuit the acpl-302j has non-inverting gate control inputs, an open drain fault, and uvlo outputs suitable for wired or applications. the recommended application circuit shown in figure 3 illustrates a typical gate drive implementation using the acpl-302j. the two supply bypass capacitors (0.1 m f) provide the large transient currents necessary during a switching tran - sition. the desat diode and 220 pf blanking capacitor are the necessary external components for the fault detection circuitry. the gate resistor (10 ? ) serves to limit gate charge current and indirectly controls the igbt collector voltage rise and fall times. the open collector fault and uvlo outputs have a passive 10 k ? pull-up resistor and a 330 pf fltering capacitor. 4
figure 3. typical gate drive circuits with desat current sensing using acpl-302j note. component value subject to change with varying application requirements operation of integrated flyback controller the primary control block implements direct duty cycle control logics for line and load regulation. primary winding currents are sensed and limited to prevent transformer short circuit failure from damaging the primary switch. secondary output voltage v cc2 is also sensed and fed back to the primary control circuits. v cc2 over voltage can be detected and the primary switch is turned of to protect secondary overvoltage failure. the maximum pwm duty cycle is designed to be around 55% to ensure discontinu - ous operation mode under a high load condition. for a complete isolated dc-dc converter, connect a discrete transformer to acpl-302j, as in figure 3. keep the led of when you are powering up v cc1 . to ensure proper operation of the dc-dc converter, a fast v cc1 rise time ( 5 ms) is preferred for a soft start function to control the inrush current. the average pwm switching frequency of the primary switch (sw) is dithered typically in a range of 6%. this frequency dithering feature helps to achieve better emi performance by spreading the switching and its harmonics over a wider band. reference dc/dc circuit figure 3 shows a reference circuit for dc/dc fyback con - version including the compensation network at pin 4, comp. this compensation network is referenced to a nominal transformer of l p = 60 m h, l s =260 m h. for v cc1 = 8 v to 18 v, this circuit will nominally support a secondary-side load of up to 60 ma (including i cc2 ) at the regulated v cc2 voltage. for v cc1 = 6 v to 8v, the supported load will be up to 40 ma. users must further characterize the dc/dc fyback con - version across their target operating conditions and chosen components to ensure that the required load can be supported. v in = 8 v - 18 v 10 f l p l s 220 nf 2 k? + 5v led2+ v cc2 v ee2 v ee2 vo ssd/clamp v e sw v ee1 an ca /fault /uvlo desat v cc1 comp 470k? 10k? 10? 330 pf 22 nf 330 pf 330 pf 0.1 f 130? 1 k? 220 pf acpl-302j 1 k? 130? v gate i f 10 f c g e 10 f c 10k? 5
description of gate driver and miller clamping the gate driver is directly controlled by the led current. when the led current is driven high, acpl-302j can then deliver a 2.5 a sourcing current to drive the igbts gate. when the led is switched of, the gate driver can provide a 2.5 a sinking current to quickly switch of the gate. the additional miller clamping pull-down transistor is activated when the output voltage reaches about 2 v with respect to v ee2 to provide a low impedance path to the miller current, as shown in figure 6. description of under voltage lock out insufcient gate voltage to igbt can increase turn on resistance of igbt, resulting in large power loss and igbt damage due to high heat dissipation. acpl-302j monitors the output power supply constantly. when output power supply is lower than under voltage lockout (uvlo) threshold gate driver output will shut of to protect igbt from low voltage bias. during power up, the uvlo feature forces the acpl - 302js output low to prevent an unwanted turn-on at lower voltage. description of over-voltage protection if v cc2 is greater than the specifed v cc2 overvoltage protection threshold, then the transistor at the sw pin on the primary side will shut down and the dc/dc fyback conversion will stop. v cc1 v cc2 led i f v o /fault /uvlo t uvlo_on t uvlo_off t phl_uvlo t plh_uvlo v uvlo+ v uvlo - v cc1_th desat fault detection blanking time after the igbt is turned on, the desat fault detection circuitry must remain disabled for a short time period to allow the collector voltage to fall below the desat threshold. this time period, called the total desat blanking time, is con - trolled by the both internal desat blanking time t desat(blanking) and external blanking time, determined by the internal charge current, the desat voltage threshold, and the external desat capacitor. the total blanking time is calculated in terms of internal blanking time (t desat(blanking) ), external capacitance (c blank ), fault threshold voltage (v desat ), and desat charge current (i chg ) as t blank = t desat(blanking) + c blank v desat / i chg figure 4. gate drive signal behavior figure 5. circuit behaviors at power-up and power down i f v o v gate 6
during a short circuit: 1. desat terminal monitors igbts v ce voltage. 2. when the voltage on the desat terminal exceeds 7 v, the igbt gate voltage (v gate ) is slowly lowered by soft shutdown pin ssd. output driver v o enters into high impedance state. 3. output driver v o ignores all pwm commands during mute time t desat(mute) . 4. fault output goes low, notifying the microcontroller of the fault condition. 5. microcontroller takes appropriate action. 6. when t desat(mute) expires, the led input needs to be kept low for t desat(reset) before fault condition can be cleared. fault status will return to high. 7. output starts to respond to led input after fault condition is cleared. figure 6. circuit behaviors during desaturation event t desat (/fault) t t desat (blanking) t desat (90%) i f v desat v /fault v o state ssd/clamp state v gate hi-z c l a m p clamp t desat (mute) c l a m p v desat_th s s d hi-z hi-z hi-z desat (reset) 7
regulatory information the acpl-302j is approved by the following organizations: ul csa iec/en/din en 60747-5-5 approved under ul 1577, component recognition program up to v iso = 5000 v rms expected before product release. approved under csa component ac - ceptance notice #5, file ca 88324. approved under: iec 60747-5-5: en 60747-5-5: din en 60747-5-5: iec/en/din en 60747-5-5 insulation characteristics description symbol units installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 600 v rms for rated mains voltage 1000 v rms i C iv i C iv i - iv i - iii climatic classifcation 40/105/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 1230 v peak input-to-output test voltage, method b v iorm 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 2306 v peak input-to-output test voltage, method a v iorm 1.6 = v pr , type and sample test with t m = 10 sec, partial discharge < 5 pc v pr 1968 v peak highest allowable overvoltage (transient overvoltage t ini = 60 sec) v iotm 8000 v peak safety-limiting values C maximum values allowed in the event of a failure, (also see figure 7) case temperature input power output power ts p s, input p s,output 175 400 1200 c mw mw insulation resistance at t s , v io = 500 v r s > 10 9 ? notes: 1. isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in the application. surface mount classifcation is class a in accordance with ceccoo802. 2. refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulation section iec/en/ din en 60747-5-5, for a detailed description of method a and method b partial discharge test profles. figure 7. dependence of safety limiting values on temperature p s ? power ? mw 0 0 t s ? case temperature ? c 200 1200 800 25 1400 50 75 100 400 150 175 125 200 600 1000 p s , output p s , input 8
insulation and safety related specifcations parameter symbol value unit conditions minimum external air gap (external clearance) l(101) 8.3 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (external creepage) l(102) 8.3 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti > 175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110) absolute maximum ratings unless otherwise specifed, all voltages at input ic reference to v ee1 , all voltages at output ic reference to v ee2 . parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 105 c 1 ic junction temperature t j 125 c average input current i f(avg) 20 ma peak transient input current (< 1 m s pulse width, 300 pps) i f(tran) 1 a reverse input voltage (v ca -v an ) v r 6 v primary switch voltage v sw 36 v input supply voltage v cc1 -0.5 26 v 33 /uvlo pin voltage v /uvlo -0.5 6 v /fault pin voltage v /fault -0.5 6 v /fault output current (sinking) i /fault 10 ma /uvlo output current (sinking) i /uvlo 10 ma output supply voltage v cc2 - v ee2 -0.5 25 v negative output supply voltage v ee2 - v e -15 0.5 v 2 positive output supply voltage v cc2 - v e -0.5 25 v gate drive output voltage v o(peak) - v ee2 -0.5 v cc2 +0.5 v miller clamping pin voltage v clamp - v ee2 -0.5 v cc2 +0.5 v desat voltage v desat - v e C 0.5 10 v 3 peak output current |i o(peak) | 2.5 a 4 output ic power dissipation p o 580 mw 1 input ic power dissipation p i 180 mw 9
recommended operating conditions parameter symbol min. max. units notes operating temperature t a -40 105 c input ic supply voltage v cc1 8 18 v 5 total output ic supply voltage v cc2 C v ee2 18 22 v 6 positive output ic supply voltage v cc2 C v e 15 25 7 negative output ic supply voltage v ee2 -v e -10 0 7 input led turn on current i f(on) 10 16 ma input led turn of voltage (v an -v ca ) v f(off) -5.5 0.8 v pwm duty cycle d max 50 % peak sw current i sw_pk 1.3 a input pulse width t on(led) 500 ns electrical specifcations unless otherwise specifed, all minimum/maximum specifcations are at recommended operating conditions, all voltages at input ic are referenced to v ee1 , all voltages at output ic referenced to v ee2 . all typical values at t a = 25 c, v cc1 = 12 v, v cc2 -v ee2 = 20 v, v e -v ee2 = 0 v. parameter symbol min typ max units test conditions fig. note dcdc flyback converter pwm switching frequency f pwm 40 60 80 khz maximum pwm duty cycle d 56 % 8 v cc1 turn-on threshold v cc1_th 6 v sw turn-on resistance r on_sw 0.9 ? i sw = 1.3 a 9 regulated v cc2 voltage v cc2 18 20 22 v i comp = 0 a 10 sw overcurrent protection threshold i sw_th 2 a v cc2 overvoltage protection threshold v ov_th 24 v ic supply current input supply current i cc1 4.0 6.1 ma 11 output low supply current i cc2l 10.5 13.2 ma i f = 0 ma v cc2 = 20 v 12 output high supply current i cc2h 10.6 13.6 ma i f = 10 ma v cc2 = 20 v 12 logic input and output led forward voltage (v an C v ca ) v f 1.25 1.55 1.85 v i f = 10 ma 13 led reverse breakdown voltage (v ca C v an ) v br 6 v i f = -10 m a led input capacitance c in 90 pf led turn-on current threshold low-to-high i th+ 2.4 6.6 ma v o = 5 v 14 led turn-on current threshold high-to-low i th- 1.8 6.4 ma v o = 5 v 14 led turn-on current hysteresis i th_hys 0.6 ma fault logic low output current i fault_l 4.0 9.0 ma v /fault = 0.4 v fault logic high output current i fault_h 20 m a v /fault = 5 v uvlo logic low output current i uvlo_l 4.0 9.0 ma v /uvlo = 0.4 v uvlo logic high output current i uvlo_h 20 m a v /uvlo = 5 v continued on next page... 10
electrical specifcations (continued) unless otherwise specifed, all minimum/maximum specifcations are at recommended operating conditions, all voltages at input ic are referenced to v ee1 , all voltages at output ic referenced to v ee2 . all typical values at t a = 25 c, v cc1 = 12 v, v cc2 -v ee2 = 20 v, v e -v ee2 = 0 v. parameter symbol min typ max units test conditions fig. note gate driver high level output current i oh -1.9 -0.75 a v o = v cc2 - 3 v 15 4 low level output current i ol 1.0 2.3 a v o = v ee2 + 2.5 v 16 4 high level output voltage v oh v cc2 C0.5 v cc2 C0.15 v i o = -100 ma 8,9,10 low level output voltage v ol 0.1 0.5 v i o = 100 ma v source to high level output propagation delay time t plh 50 120 250 ns v source = 5 v r f = 260 ?, r g = 10 ? c load = 10 nf f = 10 khz duty cycle = 50% 17,22 11 v source to low level output propagation delay time t phl 50 160 250 ns 17,22 12 pulse width distortion pwd -40 40 140 ns 13,14 dead time distortion (t plh -t phl ) dtd -160 -40 60 ns 14,15 10% to 90% rise time t r 70 ns 90% to 10% fall time t f 35 ns output high level common mode transient immunity |c mh | 30 >50 kv/ m s t a =25 c, i f = 10 ma, v cm =1500 v 23 16 output low level common mode transient immunity |c ml | 30 >50 kv/ m s t a = 25 c, i f = 0 ma, v cm =1500 v 24 17 active miller clamp and soft shutdown low level soft shutdown current during fault condition i ssd 22 35 55 ma v ssd C v ee2 = 14 v 18 clamp threshold voltage v th_clamp 2.0 3.0 v clamp low level sinking current i clamp 0.5 2.0 a v clamp = v ee2 + 2.5 v v cc2 uvlo protection (uvlo voltage v uvlo reference to v e ) v cc2 uvlo threshold low to high v uvlo+ 10.9 12.5 13.8 v v o > 5 v 10,18 v cc2 uvlo threshold high to low v uvlo- 10.0 11.3 12.8 v v o < 5 v 10,19 v cc2 uvlo hysteresis v uvlo_hys 1.2 v 10 v cc2 to uvlo high delay t plh_uvlo 15 m s 20 v cc2 to uvlo low delay t phl_uvlo 10.7 m s 21 v cc2 uvlo to v out high delay t uvlo_on 5.3 m s 22 v cc2 uvlo to v out low delay t uvlo_off 1.1 m s 23 continued on next page... 11
electrical specifcations (continued) unless otherwise specifed, all minimum/maximum specifcations are at recommended operating conditions, all voltages at input ic are referenced to v ee1 , all voltages at output ic referenced to v ee2 . all typical values at t a = 25 c, v cc1 = 12 v, v cc2 -v ee2 = 20 v, v e -v ee2 = 0 v. parameter symbol min typ max units test conditions fig. note desaturation protection (desat voltage v desat reference to v e ) desat sensing threshold v desat 6.2 7.0 7.8 v 19 10 desat charging current i chg -1.1 -0.9 -0.65 ma v desat = 2 v 20 desat discharging current i dschg 20 53 ma v desat = 8 v 21 v cc2 during fault condition v cc2(fault) 19 v i cc2 during fault condition i cc2(fault) 11.6 ma v cc2 = 20 v internal desat blanking time t desat(blanking) 0.3 0.6 1.1 m s c ssd =10 nf 24 desat sense to 90% ssd delay t desat(90%) 0.6 m s 25 desat sense to 10% ssd delay t desat(10%) 6.0 m s 26 desat to low level /fault signal delay t desat(/fault) 7.0 m s 27 output mute time due to desat t desat(mute) 2.3 3.2 ms 28 time for input kept low before fault reset to high t desat(reset) 2.3 3.2 ms 29 package characteristics parameter symbol min. typ. max. units test conditions note input-output momentary withstand voltage v iso 5000 v rms rh < 50%, t = 1 min. t a = 25 c 30, 31, 32 resistance (input-output) r i-o 10 14 ? v i-o = 500 v dc 32 capacitance (input-output) c i-o 1.3 pf f = 1 mhz 32 thermal coefcient between led and input ic a ei 35.4 c/w thermal coefcient between led and output ic a eo 33.1 c/w thermal coefcient between input ic and output ic a io 25.6 c/w thermal coefcient between led and ambient a ea 176.1 c/w thermal coefcient between input ic and ambient a ia 92 c/w thermal coefcient between output ic and ambient a oa 76.7 c/w 12
notes: 1. output ic power dissipation is derated linearly above 80 c from 580 mw to 260 mw at 105 c. 2. this supply is optional. required only when negative gate drive is implemented. 3. maximum 500 ns pulse width if peak v desat > 10 v. 4. maximum pulse width = 1 m s, maximum duty cycle = 1%. 5. in most applications v cc1 will be powered up frst (before v cc2 ) and powered down last (after v cc2 ). this is desirable for maintaining control of the igbt gate. in applications where v cc2 is powered up frst, it is important to ensure that input remains low until v cc1 reaches the proper operating voltage to avoid any momentary instability at the output during v cc1 ramp-up or ramp-down. 6. 15 v is the recommended minimum operating positive supply voltage (v cc2 - v e ) to ensure adequate margin in excess of the maximum v uvlo+ threshold of 13.5 v. 7. if dc-dc controller is not used for powering output ic. 8. for high level output voltage testing, v oh is measured with a dc load current. when driving capacitive loads, v oh will approach v cc as i oh approaches zero. 9. maximum pulse width = 1.0 ms, maximum duty cycle = 20%. 10. once v out of the acpl-302j is allowed to go high (v cc2 - v e > v uvlo ), the desat detection feature of the acpl-302j will be the primary source of igbt protection. uvlo is needed to ensure desat is functional. once v cc2 exceeds v uvlo+ threshold, desat will remain functional until v cc2 is below v uvlo- threshold. thus, the desat detection and uvlo features of the acpl-302j work in conjunction to ensure constant igbt protection. 11. t plh is defned as propagation delay from 50% of led input i f to 50% of high level output. 12. t phl is defned as propagation delay from 50% of led input i f to 50% of low level output. 13. pulse width distortion (pwd) is defned as (t phl C t plh ) of any given unit. 14. as measured from i f to v o . 15. dead time distortion (dtd) is defned as (t plh - t phl ) between any two acpl-302j parts under the same test conditions. 16. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15 v). a 330 pf and a 10 k ? pull-up resistor is needed in fault and uvlo detection mode. 17. common mode transient immunity in the low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v). a 330 pf and a 10 k ? pull-up resistor is needed in fault and uvlo detection mode. 18. this is the increasing (i.e. turn-on or positive going direction) of v cc2 - v e . 19. this is the decreasing (i.e. turn-of or negative going direction) of v cc2 - v e . 20. the delay time when v cc2 exceeds uvlo+ threshold to uvlo positive-going edge. 21. the delay time when v cc2 falls below uvlo- threshold to uvlo negative-going edge. 22. the delay time when v cc2 exceeds uvlo+ threshold to 50% of high level output. 23. the delay time when v cc2 falls below uvlo- threshold to 50% of low level output. 24. the delay time for acpl-302j to respond to a desat fault condition without any external desat capacitor. 25. the amount of time from when desat threshold is exceeded to 90% of v gate at mentioned test conditions. 26. the amount of time from when desat threshold is exceeded to 10% of v gate at mentioned test conditions. 27. the amount of time from when desat threshold is exceeded to fault output low C 50% of v cc1 voltage. 28. the amount of time when desat threshold is exceeded, output is mute to led input. 29. the amount of time when desat mute time is expired, led input must be kept low for fault status to return to high. 30. in accordance with ul1577, each optocoupler is proof-tested by applying an insulation test voltage 6000 v rms for 1 second. 31. the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating, refer to your equipment level safety specifcation or iec/en/din en 60747-5-5 insulation characteristics table. 32. device considered a two-terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 33. max 34v, 10 pulses, 400ms pulse width, 60s intervals. p c b top s i de p c b bottom s i de v e e 1 vee1 vee2 40 mm 6 0 mm vee1 vee2 4 0 mm 60 mm thermal characteristics are based on the ground planes layout of the evaluation pcb. 13
notes on thermal calculation application and environmental design for acpl-302j needs to ensure that the junction temperature of the internal ics and led within the gate driver optocoupler does not exceed 125 c. the following equations are to calculate the maximum power dissipation and the corresponding efect on junction temperatures. led junction temperature = a ea *p e + a ei *p i + a eo *p o + t a input ic junction temperature = a ei *p e + a ia *p i + a io *p o + t a output ic junction temperature = a eo *p e + a io *p i + a oa *p o + t a p e - led power dissipation p i - input ic power dissipation p o - output ic power dissipation calculation of led power dissipation led power dissipation, p e = i f(led) (recommended max) * v f(led) * duty cycle example: p e = 16 ma * 1.25 * 50% duty cycle = 10 mw calculation of input ic power dissipation input ic power dissipation, p i = p i(static) + p i(sw) p i(static) - static power dissipated by the input ic p i(sw) - power dissipated in the sw pin due to switching current of primary winding of transformer. it is calculated based on averaging switching current and turn-on resistance of sw. where p i(static) = i cc1 * v cc1 p i(sw) = i sw(avg) 2 * r on_sw = (i sw_pk/2 * d max * v in_min /v in ) 2 * r on_sw the highest input power dissipation is at minimum v in , where the average current of sw pin is highest, v in = v cc1 = v in(min) = 8 v. p i(static) = 6 ma * 8 v = 48 mw p i(sw) = (1.3 a/2 * 50% * 8v/8v ) 2 * 0.9 ? = 95 mw p i = p i(static) + p i(sw) = 48 mw + 95 mw =143 mw calculation of output ic power dissipation output ic power dissipation, p o = v cc2 (recommended max) * i cc2 (max) + p hs + p ls p hs - high side switching power dissipation p ls - low side switching power dissipation p hs = (v cc2 * q g * f pwm ) * r oh(max) /(r oh(max) + r gh )/2 p ls = (v cc2 * q g * f pwm ) * r ol(max) /(r ol(max) + r gl )/2 q g C igbt gate charge at supply voltage f pwm - led switching frequency r oh(max) C maximum high side output impedance - v oh(min) /i oh(min) r gh - gate charging resistance r ol(max) C maximum low side output impedance - v ol(min) /i ol(min) r gl - gate discharging resistance 14
example: r oh(max) = (v cc2 -v oh(min) )/i oh(min) = 3.0 v / 0.75 a = 4.0 ? r ol(max) = v ol(min) /i ol(min) = 2.5 v / 1 a = 2.5 ? p hs =(20 v * 1 m c * 10 khz) * 4.0 ? / (4.0 ? + 10 ? ) / 2 = 28.5 mw p ls =(20 v * 1 m c * 10 khz) * 2.5 ? / (2.5 ? + 10 ? ) / 2 = 20 mw p o = 20 v * 13.6 ma + 25 mw + 20 mw = 320.5 mw calculation of junction temperature led junction temperature = 176.1 c/w * 10 mw + 35.4 c/w * 143 mw + 33.1 c/w * 320.5 mw + t a = 17.4 c + t a input ic junction temperature = 35.4 c/w * 10 mw + 92 c/w * 143 mw + 25.6 c/w * 320.5 mw + t a = 21.7 c + t a output ic junction temperature = 33.1 c/w * 10 mw + 25.6 c/w * 143 mw + 76.7 c/w * 320.5 mw + t a = 28.5 c + t a 15
0 1 0 2 0 3 0 4 0 5 0 6 0 0 1 2 3 4 d - p w m d u t y c y c l e - % v comp - c o m p e n s a t i o n v o l t a g e - v -1 5 -1 0 -5 0 5 1 0 1 0 1 5 2 0 2 5 i comp - compensation current - a v cc - s u p p l y v o l t a g e - v -4 0 c 2 5 c 1 05 c i cc1 - i n p u t s u p p l y c u r r e n t - ma t a - temperature - c i cc2 - outp u t s u p p l y c u r r e n t - ma t a - temperature - c 0.01 0.10 1.00 10.00 100.00 1.2 1.3 1.4 1.5 1.6 v f - forward voltage - v i f - forward current - ma t a = 25 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 - 50 - 25 0 25 50 75 100 r on_sw - sw turn-on resistance - ? t a - temperature - c 0 1 2 3 4 5 6 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 10.4 10.5 10.6 10.7 10.8 10.9 11 11.1 - 50 - 25 0 25 50 75 100 icc2h icc2l figure 8. pwm duty cycle vs. v comp figure 9. r on_sw vs. temperature figure 10. i comp vs. supply voltage figure 11. i cc1 vs. temperature figure 12. i cc2 vs. temperature figure 13. i f vs. v f 16
i th - led current threshold - ma t a - temperature - c v oh - output high voltage - v i oh - output high current - a 1 1 . 5 2 2 . 5 3 3 . 5 4 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 i t h + i t h- 12 14 16 18 20 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 0 . 0 0 1 . 0 0 2 . 0 0 3 . 0 0 4 . 0 0 5 . 0 0 v ol - output low voltage - v i ol - output low current - a 0 50 100 150 200 250 - 50 - 25 0 25 50 75 100 t p - propagation delay - ns t a - temperature - c 1 5 2 0 2 5 3 0 3 5 4 0 4 5 0 5 1 0 1 5 2 0 2 5 i ssd - soft shutdown current - ma v ssd - c l a m p v o l t a g e - v 6.5 6.6 6.7 6.8 6.9 7 7.1 7.2 7.3 7.4 7.5 - 50 - 25 0 25 50 75 100 v desat - desat sensing threshold - v t a - temperature - c -4 0c 2 5c 1 0 5c 2 5c -4 0c 1 0 5c t p l h t p h l -4 0c 2 5c 1 0 5c figure 14. i th vs. temperature figure 15. v oh vs. i oh figure 16. v ol vs. i ol figure 17. t p vs. temperature figure 18. i ssd vs. v ssd figure 19. v desat threshold vs. temperature 17
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2014 avago technologies. all rights reserved. av02-4563en - july 4, 2014 0.1 f 10 260 ? signal source 0 v 5 v c load 10 nf 20 v _ + v source r f vo r g t plh t phl v o 50% led2+ vcc2 vee2 vee2 vo ssd/clamp ve sw vee1 an ca /fault /uvlo desat vcc1 comp ? 130r 10r 10 nf 20 v + _ led2+ vcc2 vee2 vee2 vo ssd/clamp ve sw vee1 an ca /fault /uvlo desat vcc1 comp high voltage pulse v cm = 1500 v 130r scope - + + - 5 v + - 10r 10 nf 20 v + _ led2+ vcc2 vee2 vee2 vo ssd/clamp ve sw vee1 an ca /fault /uvlo desat vcc1 comp scope ca high voltage pulse v cm = 1500 v 130r 130r 0.1 f 0.1 f v source 20 25 30 35 40 45 50 55 60 65 70 - 50 - 25 0 25 50 75 100 i dshg - desat discharging current - ma t a - temperature - c -1 -0.95 -0.9 -0.85 -0.8 -0.75 -0.7 - 50 - 25 0 25 50 75 100 i chg - desat charging current - ma t a - temperature - c figure 21. i chg vs. temperature figure 22. propagation delay test circuit figure 23. cmr v o high test circuit figure 24. cmr v o low test circuit figure 20. i chg vs. temperature

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